Performance information

• A method for mapping and scheduling of operations targeting register-bridge architecture LSIs with memory accesses　　　　　　　　　　　　　　　
  Sota Akashi; Kazuhito Ito
  Volume：124, Number：400, First page：108, Last page：113, Mar. 2025, [Last, Corresponding]
  Japanese, Symposium
• An implementation of convolution and pooling operations in binarized neural networks on register-bridge architecture LSI　　　　　　　　　　　　　　　
  Yuichiro Iwai; Kazuhito Ito
  Volume：124, Number：400, First page：72, Last page：77, Mar. 2025, [Last, Corresponding]
  Japanese, Symposium
• An efficient LSI implementation of popcount for convolution operations in binarized neural networks　　　　　　　　　　　　　　　
  Reiji Kikuchi; Kazuhito Ito
  Volume：124, Number：400, First page：66, Last page：71, Mar. 2025, [Last, Corresponding]
  Japanese, Symposium
• Double Modular Redundancy Design of LSI Controller for Soft Error Tolerance
  Katsutoshi OTSUKA; Kazuhito ITO
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Volume：E108-A, Number：3, First page：491, Last page：499, Mar. 2025, [Reviewed], [Last]
  Institute of Electronics, Information and Communications Engineers (IEICE), English, Scientific journal
  DOI：https://doi.org/10.1587/transfun.2024vlp0014
  DOI ID：10.1587/transfun.2024vlp0014, ISSN：0916-8508, eISSN：1745-1337
• Reduction of Static Power Consumption of LSI by Decreasing Leakage Current Paths with Equivalent Logic Expression Conversion　　　　　　　　　　　　　　　
  Kazuma Dobata, Kazuhito Ito
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：299, Last page：304, Mar. 2024, [Reviewed], [Last]
• Double Modular Redundancy Design of LSI Controller for Soft Error Tolerance　　　　　　　　　　　　　　　
  Katsutoshi OTSUKA; Kazuhito ITO
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：20, Last page：25, 2024, [Reviewed], [Last]
  Institute of Electronics, Information and Communications Engineers (IEICE), English, International conference proceedings
  ISSN：0916-8508, eISSN：1745-1337
• Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells　　　　　　　　　　　　　　　
  Yuki Imai, Shinichi Nishizawa, Kazuhito Ito
  IEICE Trans. Fundamentals, Volume：E105-A, Number：3, First page：487, Last page：496, Mar. 2022, [Reviewed], [Last]
• Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design　　　　　　　　　　　　　　　
  Yuya Kitazawa, Kazuhito Ito
  IEICE Trans. Fundamentals, Volume：E105-A, Number：3, First page：530, Last page：539, Mar. 2022, [Reviewed], [Last]
• 画像処理によるGUI 自動検証システムの構築　　　　　　　　　　　　　　　
  新井正敏, 伊藤和人
  自動車技術, Volume：76, Number：3, First page：104, Last page：110, 2022, [Reviewed]
• An Efficient LSI Implementation of the Summation of Products in Convolution Operation for Binarized Neural Networks　　　　　　　　　　　　　　　
  Mitsuru Takahashi, Kazuhito Ito
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：96, Last page：101, 2022, [Reviewed], [Last]
• 画像特徴点を使ったGUIシステムの自動実装検証の開発　　　　　　　　　　　　　　　
  新井正敏, 伊藤和人
  システム制御情報学会論文誌, Volume：34, Number：1, First page：23, Last page：25, 2021, [Reviewed]
• Energy Minimization of Double Modular Redundant Conditional Processing by Common Condition Dependency　　　　　　　　　　　　　　　
  Kazuhito Ito
  IEICE Transactions on Electronics, Volume：E103-C, Number：4, First page：181, Last page：185, 2020, [Reviewed]
• Minimization of Energy Consumption of Double Modular Redundancy Design of Conditional Processing by Common Condition Dependency　　　　　　　　　　　　　　　
  Kazuhito Ito
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：18, Last page：23, 2019, []
• Register Minimization in Double Modular Redundancy Design with Soft Error Correction by Replay　　　　　　　　　　　　　　　
  Yuya Kitazawa, Shinichi Nishizawa, Kazuhito Ito
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：192, Last page：197, 2019, []
• Analog circuit design methodology utilizing a structure of thin BOX FDSOI　　　　　　　　　　　　　　　
  Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito
  IEICE Electronics Express, Volume：16, Number：5, First page：20181136, 2019, []
• Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution　　　　　　　　　　　　　　　
  Yuto Ishihara, Shinichi Nishizawa, Kazuhito Ito
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：112, Last page：117, 2018, []
• Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution　　　　　　　　　　　　　　　
  Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa
  IEICE Trans. Fundamentals, Volume：E101-A, Number：12, First page：2271, Last page：2279, 2018, []
• Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm　　　　　　　　　　　　　　　
  Kazuhito Ito
  IEICE Transactions on Fundamentals, Volume：E99-A, Number：12, First page：2453, Last page：2462, Dec. 2016, []
• Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm　　　　　　　　　　　　　　　
  Kazuhito Ito, Hiroki Hayashi
  IEICE Transactions on Fundamentals, Volume：E99-A, Number：12, First page：2507, Last page：2510, Dec. 2016, []
• Register-Bridge Architecture and its Application to Multiprocessor Systems　　　　　　　　　　　　　　　
  Takafumi Fujii, Shinichi Nishizawa, Kazuhito Ito
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：10, Last page：15, 2016, []
• A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining　　　　　　　　　　　　　　　
  Kazuhito ITO
  IEICE Transactions on Fundamentals, Volume：E98-A, Number：5, First page：1058, Last page：1066, May 2015, []
• Minimization of Register Area Cost for Soft-Error Correction in Low Energy DMR Design　　　　　　　　　　　　　　　
  Kazuhito Ito, Takumi Negishi
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：56, Last page：61, 2015, []
• Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage　　　　　　　　　　　　　　　
  Kazuhito Ito
  IEICE Trans. Fundamentals, Volume：E97-A, Number：12, First page：2530, Last page：2539, Dec. 2014, []
• Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders　　　　　　　　　　　　　　　
  Kazuhito Ito, Ryoto Shirasaka
  IEICE Transactions on Fundamentals, Volume：E96-A, Number：12, First page：2680, Last page：2688, Dec. 2013, []
• 低消費電力シンドローム基本方程式求解アーキテクチャ　　　　　　　　　　　　　　　
  伊藤和人
  電子情報通信学会論文誌, Volume：J96-A, Number：9, First page：691, Last page：694, Sep. 2013, []
• 高速ヴィタビ復号の先見ACS計算レイテンシ削減手法　　　　　　　　　　　　　　　
  伊藤和人, 白坂龍人, 大西秀児
  電子情報通信学会論文誌, Volume：J96-A, Number：9, First page：695, Last page：698, Sep. 2013, []
• A Parallel Simulated Annealing Algorithm with Look-Ahead Neighbor Solution Generation　　　　　　　　　　　　　　　
  Yusuke Ota, Kazuhito Ito
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：106, Last page：111, 2013, []
• A Low Energy Full TMR Design Method with Optimized Selection of Time/Space TMR Mode and Supply Voltage　　　　　　　　　　　　　　　
  Kazuhito Ito, Yuki Hayashi
  Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, First page：334, Last page：339, 2013, []
• A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities　　　　　　　　　　　　　　　
  Kazuhito Ito, Kazuhiko Kameda
  IPSJ Transactions on System LSI Design Methodology, Volume：6, First page：60, Last page：70, 2013, []
• An Area-Time Efficient Key Equation Solver with Euclidean Algorithm for Reed-Solomon Decoders　　　　　　　　　　　　　　　
  Kazuhito Ito
  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Volume：E96A, Number：2, First page：609, Last page：617, 2013, []
  Reed-Solomon (RS) code is one of the well-known and widely used error correction codes. Among the components of a hardware RS decoder, the key equation solver (KES) unit occupies a relatively large portion of the hardware. It is important to develop an efficient KES architecture to implement efficient RS decoders. In this paper, a novel polynomial division technique used in the Euclidean algorithm (EA) of the KES is presented which achieves the short critical path delay of one Galois multiplier and one Galois adder. Then a KES architecture with the EA is proposed which is efficient in the sense of the product of area and time.
  IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
  DOI：https://doi.org/10.1587/transfun.E96.A.609
  DOI ID：10.1587/transfun.E96.A.609, ISSN：0916-8508, eISSN：1745-1337
• Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors　　　　　　　　　　　　　　　
  Kazuhito Ito; Takuya Numata
  IEICE TRANSACTIONS ON ELECTRONICS, Volume：E96C, Number：4, First page：463, Last page：472, 2013, []
  In order to reduce the dynamic energy dissipation in CMOS LSIs, it is effective to reduce the frequency of value changes of the signals. In this paper, a data expression with the valid digit and lower digit overflow information is proposed to suppress unnecessary signal changes in integer functional units and registers of general purpose processors. Experimental results show that the proposed method reduces the energy dissipation by 9.8% for benchmark programs.
  IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
  DOI：https://doi.org/10.1587/transele.E96.C.463
  DOI ID：10.1587/transele.E96.C.463, ISSN：1745-1353
• A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes　　　　　　　　　　　　　　　
  Kazuhito Ito
  IEICE Transactions on Fundamentals, Volume：E95-A, Number：4, First page：767, Last page：775, Apr. 2012, []
• A Trace-Back Method with Source States and its Application to Viterbi Decoders of Low Power and Short Latency　　　　　　　　　　　　　　　
  Kazuhito Ito
  Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2012, First page：372, Last page：377, Mar. 2012, []
• A Method of Power Supply Voltage Assignment and Scheduling of Operations to Reduce Energy Consumption of Error Detectable Computations　　　　　　　　　　　　　　　
  Yuki Suda, Kazuhito Ito
  Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2012, First page：420, Last page：424, Mar. 2012, []
• A Processor Accelerator for Software Decoding of Reed-Solomon Codes　　　　　　　　　　　　　　　
  Kazuhito ITO, Keisuke NASU
  IEICE Transactions on Fundamentals, Volume：E95-A, Number：5, First page：884, Last page：893, 2012, []
• A Processor Accelerator for Software Decoding of BCH Codes　　　　　　　　　　　　　　　
  Kazuhito Ito
  IEICE Transactions on fundamentals of electronics, communications and computer sciences, Volume：E93-A, Number：7, First page：1329, Last page：1337, Jul. 2010, []
  電子情報通信学会
• A resource binding method to reduce data communication power dissipation on LSI　　　　　　　　　　　　　　　
  Hidekazu Seto; Kazuhito Ito
  IPSJ Transactions on System LSI Design Methodology, Volume：3, First page：257, Last page：267, 2010, []
  The energy dissipation by data communications on a LSI chip depends on the layout of modules as well as how data are communicated among modules. The requirement of data communications are determined by the schedule of computations and by the resource binding of computations to functional units and data to registers. In this paper, a method of resource binding is proposed to derive a binding which is able to obtain the floorplan with reduced energy dissipation by data communications. © 2010 Information Processing Society of Japan.
  情報処理学会
  DOI：https://doi.org/10.2197/ipsjtsldm.3.257
  DOI ID：10.2197/ipsjtsldm.3.257, ISSN：1882-6687
• FPGA を用いた並列 FFT の実現　　　　　　　　　　　　　　　
  伊藤和人
  埼玉大学地域オープンイノベーションセンター紀要, Volume：1, First page：67, Last page：72, 2009
  埼玉大学地域オープンイノベーション
• Energy Dissipation Reduction of Arithmetic Operations with Valid Digits　　　　　　　　　　　　　　　
  Kazuhito Ito; Yorito Nagasaka
  Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2009, First page：35, Last page：40, 2009, []
• Reducing power dissipation of data communications on LSI with scheduling exploration　　　　　　　　　　　　　　　
  Kazuhito Ito; Hidekazu Seto
  IPSJ Transactions on System LSI Design Methodology, Volume：2, First page：53, Last page：63, 2009, []
  Power dissipation by data communications on LSI depends on not only the binding and floorplan of functional units and registers but how data communications are executed. Data communications depend on the binding, and the binding depends on the schedule of operations. Therefore, it is important to obtain the best schedule which leads to the best binding and floorplan to minimize the power dissipated by data communication. In this paper a schedule exploration method is presented to search the best one which achieves the minimized energy dissipation of data communications. © 2009 Information Processing Society of Japan.
  DOI：https://doi.org/10.2197/ipsjtsldm.2.53
  DOI ID：10.2197/ipsjtsldm.2.53, ISSN：1882-6687
• スケジューリングとバス分割によるＶＬＳＩ消費電力削減　　　　　　　　　　　　　　　
  伊藤和人
  総合研究機構研究プロジェクト研究成果報告書, Volume：第5号(18年度), First page：689, Last page：690, 2007
  埼玉大学総合研究機構
• A BCH Accelerator for Application Specific Processors　　　　　　　　　　　　　　　
  Kazuhito Ito
  Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies 2007, First page：115, Last page：121, 2007, []
• Schedule Exploration for Minimizing Energy Consumption by Data Communications　　　　　　　　　　　　　　　
  Kazuhito Ito
  Proceedings of the Workshop on synthesis And System Integration of Mixed Information Technologies 2006, Volume：-, First page：308, Last page：313, 2006, []
• 自己ハザードによりステージ数を節約したCISCパイプラインプロセッサの自動生成　　　　　　　　　　　　　　　
  王佶, 山口達彦, 伊藤和人
  第18回回路とシステム軽井沢ワークショップ論文集, Volume：-, First page：569, Last page：574, 2005, []
• Rapid and precise instruction set evaluation for.application specific processor design　　　　　　　　　　　　　　　
  M Masuda; K Ito
  2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, Volume：-, First page：6210, Last page：6213, 2005, []
  The selection of instruction set of a processor greatly influences the processor hardware and execution of software in speed, area, and power. Evaluation of instruction set is an important task in designing a processor specific to a given application. In this paper, a technique to rapidly and precisely evaluate instruction sets for the given application is proposed. It uses efficient branch and bound to explore the combination of instructions and evaluates the execution steps by task scheduling. The results show the proposed technique efficiently evaluates instruction sets for assumed processor hardware.
  IEEE
  DOI：https://doi.org/10.1109/ISCAS.2005.1466059
  DOI ID：10.1109/ISCAS.2005.1466059, ISSN：0271-4302
• Spatially unequal error protection in video coding for low SNR channels　　　　　　　　　　　　　　　
  K Ito; H Yamamoto
  2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, Volume：I, First page：249, Last page：252, 2004, []
  There is an increasing demand for video applications on mobile communication channels which are rather narrow bandwidth and low signal-to-noise ratio. Before transmission, video signals are coded to reduce the amount of data and channel coded with error correction codes to minimize the influence of noise during the data transfer. The channel coding usually sacrifices the effective bandwidth and it may result in degradation of the decoded video quality. In this paper, we propose an error protection scheme for video codes where the strength of error protection is spatially changed according to the importance of the video contents.
  IEEE
• New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec　　　　　　　　　　　　　　　
  T Adiono; T Isshiki; C Honsawek; K Ito; DJ Li; H Kunieda
  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Volume：E85A, Number：6, First page：1396, Last page：1407, 2002, []
  A new H.263+ rate control method that has very low encoder-decoder delay, small buffer and low computational complexity for hardware realization is proposed in this paper. This method focuses on producing low encoder-decoder delay in order to solve the lip synchronization problem. Low encoder-decoder delay is achieved by improving target bit rate achievement and reducing processing delay. The target bit rate achievement is improved by allocating an optimum frame encoding bits, and employing a new adaptive threshold of zero vector motion estimation. The processing delay is reduced by simplifying quantization parameter computation, applying a new non-zero coefficient distortion measure and utilizing previous frame information in current frame encoding. The simulation results indicate very large number skipped frames reduction in comparison with the test model TMN8. There were 80 skipped frames less than that of TMN8 within a 380 frame sequence during encoding of a very high movement video sequence. The 27kbps target bit rate is achieved with insignificant difference for various types of video sequences. The simulation results also show that our method successfully allocates encoding bits, maintains small data at the encoder buffer and avoids buffer from overflow and underflow.
  IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
  ISSN：0916-8508, eISSN：1745-1337
• System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications(Special Section on VLSI Design and CAD Algorithms)　　　　　　　　　　　　　　　
  Chawalit Honsawek; Kazuhito Ito; Tomohiko Ohtsuka; Trio Adiono; Dongju Li; Tsuyoshi Isshiki; Hiroaki KunieDa
  IEICE transactions on fundamentals of electronics, communications and computer sciences, Volume：E84-A, Number：11, First page：2614, Last page：2622, 2001, []
  電子情報通信学会
• An overlapped scheduling method for an iterative processing algorithm with conditional operations　　　　　　　　　　　　　　　
  K Ito; T Kawasaki
  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Volume：E81A, Number：3, First page：429, Last page：438, 1998, []
  One of the ways to execute a processing algorithm in high speed is parallel processing on multiple computing resources such as processors and functional units. To identify the minimum number of computing resources, the most important is the scheduling to determine when each operation in the processing algorithm is executed. Among feasible schedules satisfying all the data dependencies in the processing algorithm, an overlapped schedule can achieve the fastest execution speed for an iterative processing algorithm. In the case of processing algorithms with operations which are executed on some conditions, computing resources can be shared by those conditional operations. In this paper, we propose a scheduling method which derives an overlapped schedule where the required number of computing resources is minimized by considering the sharing by conditional operations.
  IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
  ISSN：0916-8508, eISSN：1745-1337
• An Optimal Scheduling Method for Parallel Processing System of Array Architecture　　　　　　　　　　　　　　　
  Kazuhito Ito
  Proc. 1997 Asia and South Pacific Design Automation Conference, 1997, []
• High Speed Bit-Serial Parallel Processing on Array Architecture　　　　　　　　　　　　　　　
  Kazuhito Ito
  Proc. 1997 Asia and South Pacific Design Automation Conference, 1997, []
• Bits truncation adaptive pyramid algorithm for motion estimation of MPEG2　　　　　　　　　　　　　　　
  L Jiang; K Ito; H Kunieda
  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Volume：E80A, Number：8, First page：1438, Last page：1445, 1997, []
  In this paper, a new bits truncation adaptive pyramid (BTAP) algorithm for motion estimation is presented. The method employs bits truncation of the gray level from 8 bits to much less bits in the searching algorithm. Compared with conventional fast block matching algorithms, this method drastically improves speed for motion estimation on reduced gray-level images and preserves reasonable performance and algorithm reliability. Bits truncation concept is well combined with hierarchical pyramid algorithm in order to truncate adaptively according to image characteristics. The computation complexity is much less than that of pyramid algorithm and 3-Step motion estimation algorithm because of bit-truncated search and low overhead adaptation. Nevertheless, the PSNR property is also comparable with these two algorithms For various video sequences.
  IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
  ISSN：0916-8508, eISSN：1745-1337
• VLSI SYSTEM COMPILER FOR DIGITAL SIGNAL-PROCESSING - MODULARIZATION AND SYNCHRONIZATION　　　　　　　　　　　　　　　
  K ITO; H KUNIEDA
  IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Volume：38, Number：4, First page：423, Last page：433, 1991, []
  An overview of a VLSI system compiler that generates a highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms is described here. In line with this overview, this paper describes the modularization and the synchronization of general digital signal processing algorithms that convert them into suitable forms for the implementation by a processor array on a VLSI chip. First, signal processing algorithms are modularized into the minimum number of inner-product modules by the proposed modularization procedure. Modularizing digital signal processing algorithms with the low coefficient sensitivity parameters is also proposed. Then these modules are assigned to inner-product processors. After processors are placed and communication paths between them are routed on a VLSI chip, the synchronization procedure derives a schedule for this VLSI system. When data transfer conflict occurs on interprocessor communications links and operation execution conflict occurs on processors, how they are resolved is discussed in this paper.
  IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
  ISSN：0098-4094

• 知識ベース知識の森・電子情報通信学会　　　　　　　　　　　　　　　
  伊藤和人, [Contributor]
  2019
• 知識ベース知識の森・電子情報通信学会　　　　　　　　　　　　　　　
  伊藤和人, [Contributor]
  2019

• LSI 設計における演算スケジューリングのイジングモデル定式化　　　　　　　　　　　　　　　
  岸本拓人, 伊藤和人
  電子情報通信学会2023年総合大会論文集, Mar. 2023, [Domestic conference]
• レジスタブリッジ型LSI の力学モデルによる演算マッピング　　　　　　　　　　　　　　　
  林伸幸, 伊藤和人
  電子情報通信学会2023年総合大会論文集, Mar. 2023, [Domestic conference]
• LSIの最大消費電力を削減するスタック構造スタンダードセルライブラリ　　　　　　　　　　　　　　　
  今井祐貴、西澤真一、伊藤和人
  電子情報通信学会技術報告VLD2019-101, Feb. 2020, [Domestic conference]
• フリップフロップの記憶保持特性とIDDQテストを組み合わせたプロセスばらつき推定　　　　　　　　　　　　　　　
  西澤真一、伊藤和人
  電子情報通信学会技術報告VLD2019-102, Feb. 2020, [Domestic conference]
• 薄膜FDSOIトランジスタを用いた低電圧動作逆方向バイアス電圧生成回路　　　　　　　　　　　　　　　
  中鉢 洸太, 西澤 真一, 伊藤 和人
  DAシンポジウム2017論文集, Aug. 2018, [Domestic conference]
• 二重冗長化処理の誤り検出最少化スケジューリング手法　　　　　　　　　　　　　　　
  石原裕人,西澤真一, 伊藤和人
  Sep. 2017, [Domestic conference]
• 二重冗長化処理におけるレジスタ面積コスト最小化　　　　　　　　　　　　　　　
  伊藤和人
  Sep. 2017, [Domestic conference]
• GPGPUによるFPGA向けテクノロジマッピングの高速化　　　　　　　　　　　　　　　
  杉山方健, 西澤真一, 伊藤和人
  講演論文集, Mar. 2016, [Domestic conference]
• 乗算器数を削減した低電力シンドローム基本方程式求解手法　　　　　　　　　　　　　　　
  伊藤和人
  電子情報通信学会2014年ソサイエティ大会講演論文集, Sep. 2014, [Domestic conference]
• 先見近傍解生成による焼きなまし法の並列化手法　　　　　　　　　　　　　　　
  太田悠介, 伊藤和人
  技術研究報告VLD2012-73, Nov. 2012, [Domestic conference]
• A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System　　　　　　　　　　　　　　　
  Kazuhito Ito, Hyun-Joon Kim
  電子情報通信学会技術報告, Dec. 2009
• A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI　　　　　　　　　　　　　　　
  Hidekazu Seto, Kazuhito Ito
  電子情報通信学会技術報告, Dec. 2009
• LSIのデータ通信消費電力を削減するリソースバインディング手法　　　　　　　　　　　　　　　
  世渡秀和、伊藤和人
  電子情報通信学会技術報告, Nov. 2007
• 埼玉大学FTTLの構築　　　　　　　　　　　　　　　
  伊藤和人, 田邊俊治, 小川康一, 吉浦紀晃, 重原孝臣, 前川仁
  学術情報処理研究, Sep. 2007
• 動画像コーデックにおける主観的画質改善のための空間的不均一誤り保護　　　　　　　　　　　　　　　
  柴田太郎, 伊藤和人
  電子情報通信学会技術報告, Mar. 2007
• Schedule Exploration for Minimizing Energy Consumption by Data Communications　　　　　　　　　　　　　　　
  Proceedings of the Workshop on synthesis And System Integration of Mixed Information Technologies 2006, 2006
• フロアプランと高位合成を同時に行うLSI設計手法　　　　　　　　　　　　　　　
  大塚正臣, 伊藤和人
  電子情報通信学会技術報告, Mar. 2005
• 再構成可能加算を考慮したLSI高位設計手法　　　　　　　　　　　　　　　
  渡辺貴宏, 伊藤和人
  電子情報通信学会技術報告, Mar. 2005
• スケジューリング探索によるデータ通信消費電力削減　　　　　　　　　　　　　　　
  伊藤和人
  電子情報通信学会技術報告, 2005
• 自己ハザードによりステージ数を節約したCISCパイプラインプロセッサの自動生成　　　　　　　　　　　　　　　
  第18回回路とシステム軽井沢ワークショップ論文集, 2005
• Rapid and Precise Instruction Set Evaluation for Application Specific Processor Design　　　　　　　　　　　　　　　
  The Proceedings of IEEE International Symposium on Circuits and Systems, 2005
• 専用プロセッサ設計のためのレジスタ数を考慮した命令セット評価手法　　　　　　　　　　　　　　　
  増田雅由, 伊藤和人
  電子情報通信学会技術報告, 2005
• 専用プロセッサの命令セット評価の高速化手法　　　　　　　　　　　　　　　
  増田雅由, 伊藤和人
  電子情報通信学会技術報告, Dec. 2004
• Spatially Unequal Error Protection in Video Coding for Low SNR Channels　　　　　　　　　　　　　　　
  Proc. IEEE International Midwest Symposium on Circuits and Systems, 2004
• 自己ハザードによるCISCパイプラインプロセッサのメモリアクセスステージ低減手法　　　　　　　　　　　　　　　
  電子情報通信学会技術報告, 2003
• Bits Truncation Adaptive Pyramid Algorithm for Motion Estimation of MPEG2　　　　　　　　　　　　　　　
  IEICE Trans. Fundamentals, 1997
• An Optimal Scheduling Method for Parallel Processing System of Array Architecture　　　　　　　　　　　　　　　
  Proc. 1997 Asia and South Pacific Design Automation Conference, 1997
• High Speed Bit-Serial Parallel Processing on Array Architecture　　　　　　　　　　　　　　　
  Proc. 1997 Asia and South Pacific Design Automation Conference, 1997

• IEEE

• 動的再構成による高速並列信号処理　　　　　　　　　　　　　　　
  1999 - 2000
  Grant amount(Total)：1900000, Direct funding：1900000
  Grant number：11750303
• 信号処理用動的再構成型LSIの設計　　　　　　　　　　　　　　　
  1997 - 1998
  Grant amount(Total)：1800000, Direct funding：1800000
  Grant number：09750395
• アレー型ア-ギテクチャを有する並列信号処理システムの高位合成　　　　　　　　　　　　　　　
  1995 - 1995
  Grant amount(Total)：1100000, Direct funding：1100000
  Grant number：07750405